Cmos image sensor and method for manufacturing the same

ABSTRACT

A CIS and a method of manufacturing the same are provided. The CIS includes a device isolation layer formed on a device isolation region of a substrate of a first conductive type, the substrate including an active region and the device isolation region, the active region including a photodiode region and a transistor region; a high-concentration diffusion region of the first conductive type formed around the device isolation layer; a gate electrode formed on the active region of the substrate with a gate insulation layer interposed therebetween; a low-concentration diffusion region of a second conductive type formed on the photodiode region and spaced a predetermined distance apart from the device isolation layer; and a high-concentration diffusion region of the second conductive type formed on the transistor region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.11/528,078, filed Sep. 26, 2006, which claims the benefit under 35U.S.C. §119 of Korean Patent Application Number 10-2005-0090263 filedSep. 28, 2005, which are hereby incorporated by reference in theirentirety

FIELD OF THE INVENTION

The present invention relates to a CMOS image sensor and a method formanufacturing the same.

BACKGROUND OF THE INVENTION

In general, an image sensor is a device for converting an optical imageinto an electrical signal. Image sensors are generally classified ascharge coupled devices (CCDs) or complementary metal oxide silicon(CMOS) image sensors (CISs).

The CCD has disadvantages, such as a complex driving method and highpower consumption. Also, the CCD is manufactured through a multi-stepphotolithography process; it needs a very complicated manufacturingprocess. Therefore, the CIS is currently in the spotlight as anext-generation image sensor to resolve the disadvantages of the CCD.

The CIS includes a photodiode and a MOS transistor in a unit pixel tosequentially detect an electric signal in each unit pixel using aswitching method for displaying an image.

FIG. 1 is a sectional view of a related art CIS.

In the related art CIS, a device isolation layer 63 is formed on asubstrate 61, and then a gate 65 is formed on the substrate 61 with agate insulation layer 64 interposed therebetween.

Next, a low-concentration N ion implantation region 69 is formed at oneside of the gate 65. Spacers 70 are formed on both sidewalls of the gate65. Then, a high-concentration N⁺ ion implantation region 72 is formedat the other side of the gate 65.

However, according to the related art CIS, since an N⁻ diffusion region(i.e., a photodiode region) is included in an interface of the deviceisolation layer 63, a portion of the lattice structure collapsed fromthe trench etching process performed to form the device isolation layer63 serves as an interface electro trap and a junction leakage.Therefore, the related art CIS has a problem of weak to lowillumination.

Additionally, according to the related art CIS, the device isolation 63between pixels may not appropriately function and cause a problem ofcrosstalk where light of one pixel is transmitted into other pixels.Especially, according to the related art CIS, since the depth of atrench in the device isolation layer 63 is within 0.5 μm, electronsgenerated from the light of a long wavelength (especially, red) may notbe efficiently isolated.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a CMOS image sensorand a method for manufacturing the same that addresses and/orsubstantially obviates one or more problems, limitations, and/ordisadvantages of the related art.

An object of the present invention is to provide a CIS without ajunction leakage or an interface electron trap by preventing a latticedefect region from being converted into a photodiode region, the latticedefect region being generated when a lattice structure collapses due toan etching damage in the interface of a device isolation layer, and amethod for manufacturing the same.

Another object of the present invention is to provide a CIS that canprevent or substantially reduce crosstalk caused by light of one pixeltransmitting into other pixels, by effectively performing the separationfor device isolation between pixels.

Additional advantages, objects, and features of the invention will beset forth in part in the description which follows and in part willbecome apparent to those having ordinary skill in the art uponexamination of the following or may be learned from practice of theinvention. The objectives and other advantages of the invention may berealized and attained by the structure particularly pointed out in thewritten description and claims hereof as well as the appended drawings.

To achieve these objects and other advantages and in accordance with thepurpose of the invention, as embodied and broadly described herein,there is provided a CIS including a device isolation layer formed on adevice isolation region of a substrate of a first conductive type, thesubstrate including an active region and the device isolation region,the active region including a photodiode region and a transistor region;a high-concentration diffusion region of the first conductive typeformed around the device isolation layer; a gate electrode formed on theactive region of the substrate with a gate insulation layer interposedtherebetween; a low-concentration diffusion region of a secondconductive type formed on the photodiode region and spaced apredetermined distance apart from the device isolation layer; and ahigh-concentration diffusion region of the second conductive type formedon the transistor region.

In another aspect of the present invention, there is provided a methodfor manufacturing a CIS including forming a device isolation layer on adevice isolation region of a substrate of a first conductive type and ahigh-concentration diffusion region of the first conductive type aroundthe device isolation layer, the substrate including an active region andthe device isolation region, the active region including a photodioderegion and a transistor region; forming a gate electrode on the activeregion of the substrate with a gate insulation layer interposedtherebetween; forming a low-concentration diffusion region of a secondconductive type on the photodiode region spaced a predetermined distanceapart from the device isolation layer; and forming a high-concentrationdiffusion region of the second conductive type on the transistor region.

It is to be understood that both the foregoing general description andthe following detailed description of the present invention areexemplary and explanatory and are intended to provide furtherexplanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this application, illustrate embodiment(s) of the invention andtogether with the description serve to explain the principle of theinvention. In the drawings:

FIG. 1 is a sectional view of a related art CIS;

FIG. 2 is a sectional view of a CIS according to an embodiment of thepresent invention; and

FIGS. 3 to 10 are sectional views illustrating a method formanufacturing a CIS according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the preferred embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings.

FIG. 2 is a sectional view of a complementary metal oxide silicon imagesensor (CIS) according to an embodiment of the present invention.

Referring to FIG. 2, in the CIS, a p⁻ epi layer 102 can be formed on ap⁺⁺ conductive semiconductor substrate 101 having an active region and adevice isolation region. The active region includes a photodiode regionand a transistor region.

The active region on the semiconductor substrate 101 can be defined by adevice isolation layer 105 and a high-concentration p⁺ diffusion region106 surrounding the device isolation layer 105. In a specificembodiment, the p⁺ diffusion region 106 can be formed with a junctiondepth of 1 to 2 μm.

Here, the high-concentration p⁺ diffusion region 106 surrounds thedevice isolation layer 105 except for the top surface, and can be formeddeeper into the substrate than the device isolation layer 105.Therefore, an isolation effect for device separation between pixels ismaximized and crosstalk can be prevented.

Additionally, a lattice defect region in the interface of the deviceisolation layer 105 prevents the high-concentration p⁺ diffusion region106 from being converted into a photodiode region. Therefore, a junctionleakage or an interface electron trap can be prevented such that thesensitivity of an image sensor improves.

A gate electrode 108 can be formed on the active region of thesemiconductor substrate 101 with a gate insulation layer 107 interposedtherebetween.

A low-concentration n⁻ diffusion region 112 can be formed on thephotodiode region at one side of the gate electrode 108, and is spaced apredetermined distance apart from the device isolation layer 105.

At this point, the low-concentration n⁻ diffusion region 112 is spacedapart from the device isolation layer 105 by a thickness of thehigh-concentration p⁺ diffusion region 106. Therefore, an isolationeffect for device separation between pixels is maximized and crosstalkcan be prevented.

A low-concentration n⁻ diffusion region 110 can be formed on thetransistor region at the other side of the gate electrode. Insulationlayer sidewalls 113 can be formed on both sides surfaces of the gateelectrode 108. A high-concentration n⁺ diffusion region 115 can also beformed on the transistor region. In a further embodiment, a P⁰ diffusionregion 117 can be formed near the surface of the photodiode regionhaving the low-concentration n⁻ diffusion region 112.

FIGS. 3 to 10 are sectional views illustrating a method formanufacturing a CIS according to an embodiment of the present invention.

Hereinafter, the formation order of each component should not beconstrued as being limited to the embodiments set forth herein. Theformation order may be interchangeable between components.

Referring to FIG. 3, a low-concentration first conductive (P⁻) epi layer102 can be formed on a semiconductor substrate 101 using an epitaxialprocess. In a specific embodiment, the semiconductor substrate 101 canbe a high-concentration first conductive (P⁺⁺) single crystal silicon.

Here, the epi layer 102 can form a depletion region in a photodiodelargely and deeply such that the capability for collecting photo chargein a low-voltage photodiode increases and photo sensitivity improves.

In another embodiment, the semiconductor substrate 101 may be an n-typesubstrate having a p-type epi layer thereon.

Next, as illustrated in FIG. 4, a pad oxide layer 103 can be formed onthe semiconductor substrate 101 having the epi layer 102. A firstphotosensitive film 104 can be formed on the pad oxide layer 103.

Next, the first photosensitive film 104 can be selectively patterned todefine a device isolation region using an exposure and developmentprocess.

Here, a region where the first photosensitive film 104 is uncoveredbecomes a device isolation region. A region where the firstphotosensitive film 104 is covered becomes an active region.

Using the patterned first photosensitive film 104 as a mask, oxygen (O₂)ions can be implanted into the device isolation region of thesemiconductor substrate 101. Then, p⁺ impurity ions can be implanted athigh concentration into the device isolation region having the oxygenions. In one embodiment, the p⁺ impurity ions can be B⁺ ions.

Next, an annealing process can be performed on the semiconductorsubstrate 101 to diffuse the oxygen ions and the high-concentration p⁺impurity ions such that a device isolation layer 105 is formed on thedevice isolation region of the semiconductor substrate 101 and ahigh-concentration p⁺ diffusion region 106 is formed around the deviceisolation layer 105 simultaneously.

Here, the high-concentration p⁺ impurity ions used in thehigh-concentration p⁺ diffusion region 106 have a better diffusivitythan the oxygen ions implanted to form the device isolation layer 105.Thus, the high-concentration p⁺ impurity ions are more widely diffusedand surround the device isolation layer 105.

In a specific embodiment, the high-concentration p⁺ diffusion region 106is formed with a junction depth of 1 to 2 μm deeper than the deviceisolation layer 105.

Accordingly, the high-concentration p⁺ diffusion region 106 can surroundthe device isolation layer 105 except for the top surface, and can beformed deeper into the substrate than the device isolation layer 105.Therefore, an isolation effect for device separation between pixels ismaximized and crosstalk can be prevented.

Additionally, a lattice defect region in the interface of the deviceisolation layer 105 prevents the high-concentration p⁺ diffusion region106 from being converted into a photodiode region. Therefore, a junctionleakage or an interface electron trap can be prevented such thatsensitivity of an image sensor improves.

Next, as illustrated in FIG. 5, the first photosensitive film 104 andthe pad oxide layer 103 are removed. A gate insulation layer 107 and aconductive layer (e.g., a high-concentration polycrystal silicon layer)can be sequentially deposited on an entire surface of the epi layer 102having the device isolation layer 105.

In one embodiment, the gate insulation layer 107 can be formed using athermal oxide process or a chemical vapor deposition (CVD) method.

The conductive layer and the gate insulation layer 107 can then beselectively removed to form a gate electrode 108.

As illustrated in FIG. 6, a second photosensitive film 109 can be formedon an entire surface of the semiconductor substrate 101 having the gateelectrode 108. The second photosensitive film 109 can cover eachphotodiode region and can be patterned to expose source/drain regionsfor each transistor using an exposure and development process.

Using the patterned second photosensitive film 109 as a mask, n⁻impurity ions can be implanted at low concentration into the exposedsource/drain regions to form an n⁻ diffusion region 110.

In an embodiment, the n⁻ diffusion region 110 can be considered asoptional and does not need to be formed.

As illustrated in FIG. 7, after removing the second photosensitive film109, a third photosensitive film 111 can be formed on an entire surfaceof the semiconductor substrate 101, and can be patterned to expose eachphotodiode region using an exposure and development process.

Using the patterned third photosensitive Film 111 as a mask, n⁻ impurityions can be implanted at low concentration into the epi layer 102 toform an n⁻ diffusion region 112.

In one embodiment, the impurity ion implantation for forming the n⁻diffusion region 112 can be performed using higher energy than the n⁻diffusion region 110 in the source/drain regions. Thus, the n⁻ diffusionregion 112 can be formed deeper into the substrate than the n⁻ diffusionregion 110.

Then, after removing the patterned third photosensitive film 111 anddepositing an insulation layer on an entire surface of the semiconductorsubstrate 101, an etch back process can be performed to form sidewallinsulation layers 113 on the both sides of the gate electrode 108.

Next, as illustrated in FIG. 8, a fourth photosensitive film 114 can beformed on an entire surface of the semiconductor substrate 101 havingthe sidewall insulation layers 113. The fourth photosensitive film 114can cover each photodiode region and can be patterned to exposesource/drain regions for each transistor using an exposure anddevelopment process.

Next, using the fourth photosensitive film 114 as a mask, n⁺ impurityions can be implanted at high concentration into the exposedsource/drain regions to form the high-concentration n⁺ diffusion region115.

Next, as illustrated in FIG. 9, after removing the fourth photosensitivefilm 114 a fifth photosensitive film 116 can be formed on an entiresurface of the semiconductor substrate 101. The fifth photosensitivefilm 116 can be patterned to expose each photodiode region using anexposure and development process.

Using the patterned fifth photosensitive film 116 as a mask, p⁰ impurityions can be implanted into the epi layer 102 having thelow-concentration n⁻ diffusion region 112 to form a p⁰ diffusion region117 in the epi layer 102.

As illustrated in FIG. 10, after removing the fifth photosensitive film116, a thermal treatment process can be performed on the semiconductorsubstrate 101 to diffuse each impurity diffusion region.

Next, although processes are not shown in the drawings, after forming aplurality of metal lines in an interlayer insulation layer on theresult, a color filter layer and a microlens can be formed to completean image sensor.

According to the present invention, the CIS and a method formanufacturing the same have following effects.

After implanting oxygen ions, a device isolation layer is formed andthen a p⁺ diffusion region is formed around the device isolation layer.Therefore, an isolation effect for device separation between pixels ismaximized and crosstalk can be prevented.

Additionally, since the p⁺ diffusion region is formed around the deviceisolation layer, a lattice defect region in the interface of the deviceisolation layer prevents the high-concentration p⁺ diffusion region 106from being converted to a photodiode region. Therefore, a junctionleakage or an interface electron trap can be prevented such that thesensitivity of an image sensor improves.

It will be apparent to those skilled in the art that variousmodifications and variations can be made in the present invention. Thus,it is intended that the present invention covers the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

1. A CIS (complementary metal oxide silicon image sensor) comprising: asubstrate of a first conductive type having a device isolation regionand an active region, the active region including a photodiode regionand a transistor region; a device isolation layer formed on the deviceisolation region of the substrate; a high-concentration first conductivetype diffusion region formed around the device isolation layer; a gateelectrode formed on the active region of the substrate with a gateinsulation layer interposed therebetween; a low-concentration secondconductive type diffusion region formed on the photodiode region andspaced a predetermined distance apart from the device isolation layer;and a high-concentration second conductive type diffusion region formedon the transistor region, wherein the device isolation layer is formedby implanting oxygen ions on the device isolation region and performinga thermal treatment process on the oxygen ion implanted substrate. 2.The CIS according to claim 1, wherein the high-concentration firstconductive type diffusion region isolates the device isolation layerfrom the low-concentration second conductive type diffusion region. 3.The CIS according to claim 1, wherein the high-concentration firstconductive type diffusion region surrounds the device isolation layerexcept for a top surface of the device isolation layer.
 4. The CISaccording to claim 1, wherein the high-concentration first conductivetype diffusion region is formed deeper into the substrate than thedevice isolation layer.
 5. The CIS according to claim 4, wherein thehigh-concentration first conductive type diffusion region has a junctiondepth of 1 to 2 μm.
 6. The CIS according to claim 1, wherein thehigh-concentration first conductive type diffusion region is a p⁺impurity region.
 7. The CIS according to claim 6, wherein thehigh-concentration first conductive type diffusion region is formedimplanting B⁺ ions into the device isolation region of the substrate. 8.The CIS according to claim 1, further comprising a low-concentrationdiffusion region of the first conductive type formed on the transistorregion of the substrate.
 9. The CIS according to claim 1, wherein thelow-concentration second conductive type diffusion region is spacedapart from the device isolation layer by a thickness of thehigh-concentration first conductive type diffusion region formed aroundthe device isolation layer.